Transmission setting
| SDA_FORCE_OUT | 1: direct output, 0: open drain output. |
| SCL_FORCE_OUT | 1: direct output, 0: open drain output. |
| SAMPLE_SCL_LEVEL | This register is used to select the sample mode. 1: sample SDA data on the SCL low level. 0: sample SDA data on the SCL high level. |
| RX_FULL_ACK_LEVEL | This register is used to configure the ACK value that need to sent by master when the rx_fifo_cnt has reached the threshold. |
| MS_MODE | Set this bit to configure the module as an I2C Master. Clear this bit to configure the module as an I2C Slave. |
| TRANS_START | Set this bit to start sending the data in txfifo. |
| TX_LSB_FIRST | This bit is used to control the sending mode for data needing to be sent. 1: send data from the least significant bit, 0: send data from the most significant bit. |
| RX_LSB_FIRST | This bit is used to control the storage mode for received data. 1: receive data from the least significant bit, 0: receive data from the most significant bit. |
| CLK_EN | Reserved |
| ARBITRATION_EN | This is the enable bit for arbitration_lost. |
| FSM_RST | This register is used to reset the scl FMS. |
| CONF_UPGATE | synchronization bit |
| SLV_TX_AUTO_START_EN | This is the enable bit for slave to send data automatically |
| ADDR_10BIT_RW_CHECK_EN | This is the enable bit to check if the r/w bit of 10bit addressing consists with I2C protocol |
| ADDR_BROADCASTING_EN | This is the enable bit to support the 7bit general call function. |